參數(shù)資料
型號: SAF-XC164S-8F40F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機與C166SV2核心
文件頁數(shù): 67/72頁
文件大?。?/td> 763K
代理商: SAF-XC164S-8F40F
XC164S
Derivatives
Timing Parameters
Data Sheet
63
V1.0, 2005-01
Variable Memory Cycles
External bus cycles of the XC164S are executed in five subsequent cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
This table provides a summary of the phases and the respective choices for their
duration. The specification of the external timing depends on the period of the CPU
clock, which is called “TCP” and is used in
Table 18
Table 18
Programmable Bus Cycle Phases
(see timing diagrams)
Bus Cycle Phase
Address setup phase, the standard duration of this
phase (1
2 TCP) can be extended by 0
3 TCP
if the address window is changed
Command delay phase
Write Data setup / MUX Tristate phase
Access phase
Address / Write Data hold phase
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Parameter
tp
AB
Valid Values Unit
1
2 (5)
TCP
tp
C
tp
D
tp
E
tp
F
0
3
0
1
1
32
0
3
TCP
TCP
TCP
TCP
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