參數(shù)資料
型號(hào): SAF-XC164S-16F20F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機(jī)與C166SV2核心
文件頁數(shù): 36/72頁
文件大?。?/td> 763K
代理商: SAF-XC164S-16F20F
XC164S
Derivatives
Functional Description
Data Sheet
32
V1.0, 2005-01
Figure 7
Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the
GPT2 module
provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
T3
Mode
Control
2
n
: 1
f
SYS
2
n
: 1
f
SYS
T2
Mode
Control
GPT1 Timer T2
Reload
Capture
2
n
: 1
f
SYS
T4
Mode
Control
GPT1 Timer T4
Reload
Capture
GPT1 Timer T3
T3OTL
U/D
T2EUD
T2IN
T3IN
T3EUD
T4IN
T4EUD
Toggle FF
U/D
U/D
Interrupt
Request
(T2IR)
Interrupt
Request
(T3IR)
Interrupt
Request
(T4IR)
Mct04825_xc.vsd
T6OUT
n = 2 … 12
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