參數(shù)資料
型號(hào): SAF-XC164N-16F40F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機(jī)與C166SV2核心
文件頁數(shù): 42/68頁
文件大?。?/td> 732K
代理商: SAF-XC164N-16F40F
XC164N
Derivatives
Functional Description
Data Sheet
37
V1.0, 2005-01
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by
2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13
μ
s and 419 ms can be monitored (@ 40 MHz).
The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
3.13
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC164N with high flexibility. The master clock
f
MC
is
the reference clock signal and is output to the external system. The CPU clock
f
CPU
and
the system clock
f
SYS
are derived from the master clock either directly (1:1) or via a 2:1
prescaler (
f
SYS
=
f
CPU
=
f
MC
/ 2). See also
Section 5.1
.
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock / OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled
by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Note: At the end of an external reset (EA = ‘0’) the oscillator watchdog may be disabled
via hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration.
Clock Generation
3.14
The XC164N provides up to 79 I/O lines which are organized into six input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs (except for pin RSTOUT).
Parallel Ports
相關(guān)PDF資料
PDF描述
SAF-XC164N-8F20F 16-Bit Single-Chip Microcontroller with C166SV2 Core
SAF-XC164N-8F40F 16-Bit Single-Chip Microcontroller with C166SV2 Core
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SAF-XC164S-16F20F 16-Bit Single-Chip Microcontroller with C166SV2 Core
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