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| 型號： | SAF-C164CM-4R25F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontrol ler |
| 中文描述： | 16位單芯片Microcontrol萊爾 |
| 文件頁數(shù)： | 24/68頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | SAF-C164CM-4R25F |
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C164CM
C164SM
Data Sheet
20
V1.0, 2001-05
The Capture/Compare Unit CAPCOM2
The general purpose CAPCOM2 unit supports generation and control of timing
sequences on up to 12 channels with a maximum resolution of 16 TCL. The CAPCOM
units are typically used to handle high speed I/O tasks such as pulse and waveform
generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software
timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
Each dual purpose capture/compare register, which may be individually allocated to
either CAPCOM timer and programmed for capture or compare function, has one port
pin associated with it which serves as an input pin for triggering the capture function, or
as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (
‘
capture
’
d) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.
Table 5
Compare Modes (CAPCOM)
Compare Modes
Mode 0
Function
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Pin toggles on each compare match;
several compare events per timer period are possible
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Pin set
‘
1
’
on match; pin reset
‘
0
’
on compare time overflow;
only one compare event per timer period is generated
Two registers operate on one pin; pin toggles on each compare
match;
several compare events per timer period are possible.
Registers CC16 & CC24
pin CC16IO
Registers CC17 & CC25
pin CC17IO
Registers CC18 & CC26
pin CC18IO
Registers CC19 & CC27
pin CC19IO
Mode 1
Mode 2
Mode 3
Double
Register Mode
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