參數(shù)資料
型號(hào)： SAF-C163-L
廠商： SIEMENS AG
英文描述： 16-bit CMOS Single-Chip Microcontroller
中文描述： 16位CMOS單片機(jī)
文件頁數(shù)： 21/68頁
文件大?。?/td> 652K
代理商： SAF-C163-L
11Aug98@14:48h Intermediate Version
Semiconductor Group
19
1998-08
C163-L
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 20
μ
s and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval
after reset is 5.24 ms (@ 25 MHz).
Oscillator Watchdog
During direct drive or prescaler operation the Oscillator Watchdog (OWD) monitors the clock signal
generated by the on-chip oscillator (either with a crystal or via external clock drive). For this
operation the PLL provides a clock signal which is used to supervise transitions on the oscillator
clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and supplies the
CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic
frequency.
A low level on pin OWE disables the PLL and the OWD’s interrupt output so the clock signal is
derived from the oscillator clock in any case.
Note:
The CPU clock source is only switched back to the oscillator clock after a hardware reset.
For 3 V operation
pin OWE must always be low (OWD disabled) as the PLL cannot deliver an
appropriate clock signal in this case.
For 5 V operation
pin OWE should only be pulled low (PLL disabled) if direct drive or prescaler
operation is configured. All other configurations (PLL factors) result in direct drive operation.
相關(guān)PDF資料
PDF描述
SAF-C164CL-8R25M 16-Bit Single-Chip Microcontroller
SAF-C165-L25M 16-Bit Single-Chip Microcontroller
SAB-C165 16-Bit Single-Chip Microcontroller
SAF-C165-L25F 16-Bit Single-Chip Microcontroller
SAF-C165-LF 16-Bit Single-Chip Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAFC163-L 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-bit CMOS Single-Chip Microcontroller
SAFC164CI 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller
SAF-C164CI 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller
SAFC164CI8E25M DB 制造商:Infineon Technologies AG 功能描述:
SAF-C164CI-8E25M DB 功能描述:16位微控制器 - MCU 16-Bit Sngl-Chip 5V 25MHz OTP RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT
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