參數(shù)資料
型號: SAF-C161K
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機
文件頁數(shù): 60/66頁
文件大?。?/td> 1102K
代理商: SAF-C161K
C161K
C161O
Data Sheet
56
V2.0, 2001-01
Data float after RdCS
(with RW-delay)
1)
t
53
SR
30 +
t
F
2TCL - 20
+
2
t
A
+
t
F
1)
ns
Data float after RdCS
(no RW-delay)
1)
t
68
SR
5 +
t
F
TCL - 20
+
2
t
A
+
t
F
1)
ns
Address hold after
RdCS, WrCS
Data hold after WrCS
t
55
CC
-16 +
t
F
-16 +
t
F
ns
t
57
CC
9 +
t
F
TCL - 16
+
t
F
ns
1)
RW-delay and
t
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (Reduced Supply Voltage Range)
(cont
d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A
+
t
C
+
t
F
(100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
min.
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
min.
Unit
max.
max.
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