參數(shù)資料
型號(hào): SAF-C161K-LM3V
廠商: INFINEON TECHNOLOGIES AG
英文描述: CONNECTOR ACCESSORY
中文描述: 連接器附件
文件頁(yè)數(shù): 45/66頁(yè)
文件大小: 1102K
代理商: SAF-C161K-LM3V
C161K
C161O
Data Sheet
41
V2.0, 2001-01
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 12
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
t
A
+
t
C
+
t
F
(120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
ALE high time
t
5
CC
10 +
t
A
Memory Cycle Variables
Symbol
t
A
t
C
t
F
Values
TCL
×
<ALECTL>
2TCL
×
(15 - <MCTC>)
2TCL
×
(1 - <MTTC>)
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
min.
TCL - 10
+
t
A
TCL - 16
+
t
A
TCL - 10
+
t
A
TCL - 10
+
t
A
-10 +
t
A
Unit
max.
max.
ns
Address setup to ALE
t
6
CC
4 +
t
A
ns
Address hold after ALE
t
7
CC
10 +
t
A
ns
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
t
8
CC
10 +
t
A
ns
t
9
CC
-10 +
t
A
ns
t
10
CC
6
6
ns
t
11
CC
26
TCL + 6
ns
t
12
CC
30 +
t
C
2TCL - 10
+
t
C
ns
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