參數(shù)資料
型號(hào): SAF-C161K-L25M
廠商: INFINEON TECHNOLOGIES AG
英文描述: CONNECTOR ACCESSORY
中文描述: 連接器附件
文件頁(yè)數(shù): 40/66頁(yè)
文件大小: 1102K
代理商: SAF-C161K-L25M
C161K
C161O
Data Sheet
36
V2.0, 2001-01
AC Characteristics
Definition of Internal Timing
The internal operation of the C161K/O is controlled by the internal CPU clock
f
CPU
. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called
TCL
(see
Figure 8
).
Figure 8
Generation Mechanisms for the CPU Clock
The CPU clock signal
f
CPU
can be generated from the oscillator clock signal
f
OSC
via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
f
CPU
. This influence must
be regarded when calculating the timings for the C161K/O.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 9
associates the combinations of these three bits with the respective clock
generation mode.
MCT04826
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
TCL
TCL
TCL
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