參數(shù)資料
型號(hào): SAB83C517A-5
廠商: INFINEON TECHNOLOGIES AG
元件分類: 8位微控制器
英文描述: 8-Bit CMOS Single-Chip Microcontroller
中文描述: 8位CMOS單芯片微控制器
文件頁(yè)數(shù): 23/77頁(yè)
文件大?。?/td> 1358K
代理商: SAB83C517A-5
SAB 80C517A/83C517A-5
Semiconductor Group
22
1994-05-01
Control of XRAM in the SAB 80C517A
There are two control bits in register SYSCON which control the use and the bus operation
during accesses to the additional On-Chip RAM (XRAM).
Special Function Register SYSCON
Reset value of SYSCON is xxxx xx01B.
The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM).
If this bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external
bus. In this case the SAB 80C517A does not use the additional On-Chip RAM and is compatible
with the types without XRAM.
Addr. 0B1
H
XMAP1
XMAP0
SYSCON
Bit
Function
XMAP0
Global enable/disable bit for XRAM memory.
XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is en-
abled.
XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are per-
formed by the external bus (reset state).
XMAP1
Control bit for RD/WR signals during accesses to XRAM; this bit has no
effect if XRAM is disabled (XMAP0 = 1) or if addresses exceeding the
XRAM address range are used for MOVX accesses.
XMAP1 = 0: The signals RD and WR are not activated during accesses
to XRAM.
XMAP1 = 1: The signals RD and WR are activated during accesses to
XRAM.
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