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參數(shù)資料
| 型號： | SAB83C515A-5M18-T3 |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 18 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 19/57頁 |
| 文件大?。?/td> | 899K |
| 代理商： | SAB83C515A-5M18-T3 |
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SAB 80C515A/83C515A-5
Semiconductor Group
18
XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM
could be dangerous since indeterminate values would be read from external bus. To avoid this
the XMAP-bit is forced to '1' only by reset. Additionally, during reset an internal capacitor is
loaded. So after reset state XRAM is disabled. Because of the load time of the capacitor
XMAP0-bit once written to '0' (that is, discharging capacitor) cannot be set to '1' again by
software. On the other hand any distortion (software hang up, noise, ...) is not able to load this
capacitor, too. That is, the stable status is XRAM enabled. The only way to disable XRAM after
it was enabled is a reset.
The clear instruction for XMAP0 should be integrated in the program initialization routine before
XRAM is used. In extremely noisy systems the user may have redundant clear instructions.
The control bit XMAP1 is relevant only if the XRAM is accessed. In this case the external RD
and WR signals at P3.6 and P3.7 are not activated during the access, if XMAP1 is cleared. For
debug purposes it might be useful to have these signals and the addresses at Ports 0.2
available. This is performed if XMAP1 is set.
The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register
SYSCON and on the state of pin EA. The table 1 lists the various operating conditions. It shows
the following characteristics:
a) Use of P0 and P2 pins during the MOVX access.
Bus: The pins work as external address/data bus. If (internal) XRAM
is accessed, the data written to the XRAM can be seen on the bus in
debug mode.
I/0:
The pins work as Input/Output lines under control of their latch.
b) Activation of the RD and WR pin during the access.
c) Use of internal or external XDATA memory.
The shaded areas describe the standard operation as each 80C51 device without on-chip
XRAM behaves.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAB83C515A-5N18 | |
| SAB83C515A-5N18-T3 | 8-Bit CMOS Single-Chip Microcontroller |
| SAB83C515A-5 | 8-Bit CMOS Single-Chip Microcontroller |
| SAB80C515A-N18 | 8-Bit CMOS Single-Chip Microcontroller |
| SAB80C515A-N18-T3 | 8-Bit CMOS Single-Chip Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAB83C515A-5N18 | 制造商:Siemens 功能描述:8-BIT, MROM, 18 MHz, MICROCONTROLLER, PQCC68 |
| SAB83C515A-5N18-T3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
| SAB83C517A-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
| SAB83C517A-5N18 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
| SAB83C517A-5N18-T3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
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