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SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
Semiconductor Group
62
07.96
Figure 30
SDLC Loop
The loop is formed by connecting TxD output of one station to the RxD input of the next
one (refer to
figure 30
). This configuration is physically a loop, but logically a
point-to-multipoint configuration.
In every Secondary Station data flow from RxD to TxD is handled depending on
Secondary’s current state as follows:
Initially, RxD and TxD are connected together with gate delay (
OFF Loop
state). Data
sent out from the Primary is passed on by every Secondary to the next one. Thus, data
is transparent to all Secondaries.
After reception of an EOP sequence a Secondary can go to the
ON Loop
state. As
opposed to the Off Loop state, all data is forwarded to the next station with one bit
delay.
If a Secondary is requested (polled) by the Primary to transmit data or responses, it
has to wait for reception of a further EOP sequence. By flipping the seventh ‘1’ of the
EOP sequence to ‘0’ it generates a flag sequence and consequently all following
Secondary Stations are inhibited from sending. Simultaneously, RxD is disconnected
from TxD and transmission of a frame (or several frames) may start (
Active ON
Loop
state). After terminating transmission the station reconnects RxD to TxD. Thus,
an EOP sequence is formed and another station may start data transmission.
Processing the EOP sequences is handled automatically by the ESCC2: commands
(GLP, GALP in register CCR1) and state indications (interrupts EOP, OLP, AOLP in
register ISR1) are provided to control and monitor the state of the ESCC2 as Secondary
Station.