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參數(shù)資料
| 型號(hào)： | SAB-C515-1RM |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數(shù)： | 39/55頁 |
| 文件大?。?/td> | 268K |
| 代理商： | SAB-C515-1RM |
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Semiconductor Group
39
1997-08-01
C515
Power Saving Modes
The C515 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.
–
Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.
–
Power down mode
The operation of the C515 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/INT0.
–
Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8 th of their normal operating frequency. Slowing down the frequency significantly
reduces power consumption.
Table 8
gives a general overview of the entry and exit procedures of the power saving modes.
In the power down mode of operation,
V
CC
can be reduced to minimize power consumption. It must
be ensured, however, that
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
is restored to its normal operating level, before the power down mode is terminated.
Table 8
Power Saving Modes Overview
Mode
Entering
2-Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
ORL PCON, #20H
Occurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Hardware Reset
Power Down Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Slow Down Mode
In normal mode :
ORL PCON,#10H
ANL PCON,#0EFH
or
Hardware Reset
Internal clock rate is reduced
to 1/8 of its nominal frequency
With idle mode :
ORL PCON,#01H
ORL PCON, #30H
Occurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency
Hardware reset
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