參數(shù)資料
型號(hào): SAB-C165-L25F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機(jī)
文件頁(yè)數(shù): 63/77頁(yè)
文件大小: 1371K
代理商: SAB-C165-L25F
C165
Data Sheet
59
V2.0, 2000-12
Data valid to WR
t
22
CC
24 +
t
C
2TCL - 26
+
t
C
TCL - 10
+
t
F
- 12 +
t
F
ns
Data hold after WR
t
24
CC
15 +
t
F
ns
ALE rising edge after
RD, WR
Address hold after WR
2)
t
28
CC
ALE falling edge to CS
3)
t
38
CC
CS low to Valid Data In
3)
t
39
t
26
CC
- 12 +
t
F
ns
0 +
t
F
- 8 -
t
A
10 -
t
A
47 +
t
C
+
2
t
A
0 +
t
F
- 8 -
t
A
10 -
t
A
3TCL - 28
+
t
C
+ 2
t
A
ns
ns
ns
SR
CS hold after RD, WR
3)
t
41
CC
9 +
t
F
TCL - 16
+
t
F
TCL - 6
+
t
A
ns
ALE falling edge to
RdCS, WrCS (with RW-
delay)
ALE falling edge to
RdCS, WrCS (no RW-
delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
t
42
CC
19 +
t
A
ns
t
43
CC
- 6 +
t
A
- 6
+
t
A
ns
t
46
SR
20 +
t
C
2TCL - 30
+
t
C
3TCL
- 30
+
t
C
ns
t
47
SR
45 +
t
C
ns
t
48
CC
38 +
t
C
2TCL - 12
+
t
C
3TCL - 12
+
t
C
2TCL - 22
+
t
C
0
ns
t
49
CC
63 +
t
C
ns
t
50
CC
28 +
t
C
ns
Data hold after RdCS
t
51
SR
0
ns
Demultiplexed Bus (Reduced Supply Voltage Range)
(cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A
+
t
C
+
t
F
(100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
min.
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
min.
Unit
max.
max.
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