參數(shù)資料
型號： SAB-C161S-LM 3V AA
廠商： Infineon Technologies
文件頁數(shù)： 43/75頁
文件大?。?/td> 0K
描述： IC MICROCONTROLLER 16BIT MQFP80
標(biāo)準(zhǔn)包裝： 850
系列： C16xx
核心處理器： C166
芯體尺寸： 16-位
速度： 20MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 63
程序存儲器類型： ROMless
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 80-QFP
包裝： 帶卷 (TR)
其它名稱： B161SLM3VAAXT
C161SLM3VAABAUMA1
C161SLM3VAABXUMA1
SABC161SLM3VAAXT
SP000014946
C161S
Timing Characteristics
Data Sheet
44
V1.0, 2003-11
5
Timing Characteristics
5.1
Definition of Internal Timing
The internal operation of the C161S is controlled by the internal CPU clock
f
CPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).
Figure 10
Generation Mechanisms for the CPU Clock
The CPU clock signal
f
CPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
f
CPU. This influence must
be regarded when calculating the timings for the C161S.
Note: The example for PLL operation shown in Figure 10 refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
MCT04338
f
OSC
f
CPU
Phase Locked Loop Operation
TCL
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SABC161SLM3VAAXT 制造商:Infineon Technologies AG 功能描述:MCU 16-bit C166 CISC/RISC ROMLess 3.3V 80-Pin MQFP
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