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參數(shù)資料
| 型號： | SAB-80C517A-N18 |
| 廠商： | SIEMENS AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 8位CMOS單芯片微控制器 |
| 文件頁數(shù)： | 39/77頁 |
| 文件大?。?/td> | 1358K |
| 代理商： | SAB-80C517A-N18 |
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SAB 80C517A/83C517A-5
Semiconductor Group
38
1994-05-01
Compare
In compare mode, the 16-bit values stored in the dedicated compare registers are compared
to the contents of the timer 2 register or the compare timer register. If the count value in the
timer registers matches one of the stored value, an appropriate output signal is generated at
the corresponding pin(s) and an interrupt is requested. Three compare modes are provided:
Mode 0:
Upon a match the output signal changes from low to high.
It returns to low level at timer overflow.
Mode 1:
The transition of the output signal can be determined by software.
A timer overflow signal does not affect the compare-output.
Mode 2:
In compare mode 2 the concurrent compare output pins on Port 5 are used
as follows (see figure 9)
– When a compare match occurs with register COMSET, a high level
appears at the pins of port 5 whose corresponding bits in the mask
register SETMSK (address 0A5
H
) are set.
– When a compare match occurs in register COMCLR, a low level
appears at the pins of port 5 whose corresponding bits in the mask
register CLRMSK (address 0A6
H
) are set.
Additionally the Port 5 pins used for compare mode 2 may also be
directly written to by write instructions to SFR P5. Of course, the pins
can also be read under program control.
Compare registers CM0 to CM7 use additional compare latches when operated in mode 0.
Figure 8 shows the function of these latches. The latches are implemented to prevent from loss
of compare matches which may occur when loading of the compare values is not correlated
with the timer count. The compare latches are automatically loaded from the compare registers
at every timer overflow.
Capture
This feature permits saving of the actual timer/counter contents into a selected register upon
an external event or a software write operation. Two modes are provided to 'freeze' the current
16-bit value of timer 2 registers into a dedicated capture register.
Mode 0:
Capture is performed in response to a transition at the corresponding
port 1 pins CC0 to CC3.
Mode 1:
Write operation into the low-order byte of the dedicated capture register
causes the timer 2 contents to be latched into this register.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAB80C517A-N18 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
| SAB80C517AN18T3 | 制造商:Infineon Technologies AG 功能描述:MCU 8-Bit C500 8051 CISC ROMLess 5V 84-Pin PLCC |
| SAB80C517A-N18-T3 | 制造商:Rochester Electronics LLC 功能描述: |
| SAB80C517-M | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
| SAB80C517-M16 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
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