參數(shù)資料
型號(hào)： SAA8110G
廠商： NXP SEMICONDUCTORS
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor (DSP) for cameras(應(yīng)用于照相中的數(shù)字信號(hào)處理器)
中文描述： 0-BIT, 28.6 MHz, OTHER DSP, PQFP80
封裝： 12 X 12 X 1.40 MM, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 6/36頁(yè)
文件大?。?/td> 232K
代理商： SAA8110G
1997 Jun 13
6
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
V
DDA(DC)
V
SSA(BG)
DECOUPL
RBIAS
V
DDA(BG)
V
DDD(P1)
CLK2
FI
OUT
VSYNC
OUT
HREF
CREF/PXQ
LLC
V
SSD(P1)
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
V
DDD(P2)
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
V
SSD(P2)
V
DDD(C3)
A1/SN
RES
A0/SN
DA
SDA
V
SSD(C3)
SCL/SN
CL
V
SSD(C4)
X
IN
X
OUT
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I
I
analog supply for analog core of triple DAC
analog ground for to band gap
pin to be used for external decoupling of band gap
external bias resistor connection for band gap
analog supply for band gap
digital supply 1 for CLK2 related peripherals
output clock (CLK2 frequency is 2
×
CLK1 frequency)
field identification output pulse
vertical synchronization output
horizontal reference output for YUV-port
clock/pixel qualifier output for YUV-port
line-locked system clock output
digital ground 1 for CLK2 related peripherals
multiplex chrominance UV bit 7 (MSB)
multiplex chrominance UV bit 6
multiplex chrominance UV bit 5
multiplex chrominance UV bit 4
multiplex chrominance UV bit 3
multiplex chrominance UV bit 2
multiplex chrominance UV bit 1
multiplex chrominance UV bit 0 (LSB)
digital supply for CLK2 related peripherals
luminance Y or multiplexed YUV bit 7 (MSB)
luminance Y or multiplexed YUV bit 6
luminance Y or multiplexed YUV bit 5
luminance Y or multiplexed YUV bit 4
luminance Y or multiplexed YUV bit 3
luminance Y or multiplexed YUV bit 2
luminance Y or multiplexed YUV bit 1
luminance Y or multiplexed YUV bit 0 (LSB)
digital ground 2 for to CLK2 related peripherals
digital supply 3 for digital core and CLK1 related peripherals
I
2
C-bus address select pin A1 or SNERT reset input
I
2
C-bus address select pin A0 or SNERT data input/output
I
2
C-bus data input/output
digital ground 3 for digital core and CLK1 related peripherals
I
2
C-bus clock/SNERT clock input
digital ground 4 for digital core and CLK1 related peripherals
input crystal oscillator for subcarrier lock applications
output crystal oscillator for subcarrier lock applications
O
O
I
I
I
O
O
O
O
O
I
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
O
SYMBOL
PIN
I/O
DESCRIPTION
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