參數(shù)資料
型號: SAA7712H
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號處理
英文描述: Sound effects DSP(聲音效應數(shù)字信號處理器)
中文描述: 0-BIT, 32.544 MHz, OTHER DSP, PQFP80
文件頁數(shù): 18/44頁
文件大?。?/td> 178K
代理商: SAA7712H
1999 Aug 05
18
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
Fig.8 Configurations of the equalizer sections.
handbook, full pagewidth
MGS213
OUT0
IN0
2 channel
2 channel
1
A
2
3
4
5
OUT1
IN1
B
OUT2
IN2
C
OUT3
IN3
D
8.3.3
O
VERFLOW DETECTION
The equalizer has an overflow flag. This flag is fed to
output pin EQOV. If an overflow is detected in one of the
filter sections, the signal is clipped to the maximum
allowed level. The overflow flag is immediately set.
It remains at a HIGH-level during the remaining part of the
currentaudio sampleperiod andforthewholenextsample
period. If no overflow is detected during this next sample
period, the overflow flag goes to a LOW-level at the
beginning of the sample period after that. Otherwise, the
overflow flag remains at a HIGH-level for at least one other
audio sample period.
8.4
Clock circuit and oscillator
8.4.1
G
ENERAL DESCRIPTION
The chip has a crystal clock oscillator. It can use a crystal
at either f
xtal
= 16.384 MHz = 512
×
32 kHz or
f
xtal
= 18.432 MHz = 576
×
32 kHz in fundamental mode.
The block diagram of this Pierce oscillator is shown in
Fig.9. The active element needed to compensate for the
loss resistance of the crystal is the block Gm. This block is
placed between the external pins OSC_IN
and OSC_OUT.
The gain of the oscillator is internally controlled by the
AGC block. A sine wave with a peak-to-peak voltage close
to the oscillator power supply voltage is generated.
The AGC block prevents clipping of the sine wave and
therefore the higher harmonics are as low as possible.
At the same time, the voltage of the sine wave is as high
as possible so reducing the jitter going from sine wave to
clock signal. The sinusoidal output is converted into a
CMOS compatible clock by the comparator.
The second mode of operation shown in Fig.10, is the
slave mode which is driven by a master clock directly.
The signal to pin OSC_IN can be driven to the power
supply voltages V
DD_OSC
and V
SS_OSC
.
8.4.2
S
UPPLY OF THE CRYSTAL OSCILLATOR
The power supply connections of the oscillator are
separate from the other supply lines. This is to minimize
the feedback from the ground bounce of the chip to the
oscillator circuit. Pin V
SS_OSC
is used as the ground supply
and pin V
DD_OSC
as the positive supply.
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