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參數(shù)資料
| 型號： | SAA7284ZP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP52 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-247-1, SDIP-52 |
| 文件頁數(shù)： | 28/40頁 |
| 文件大?。?/td> | 182K |
| 代理商： | SAA7284ZP |
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1996 Oct 24
28
Philips Semiconductors
Preliminary specification
Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems
SAA7284
Notes
1.
It is assumed that all supplies are externally connected at the same source, and consequently that maximum and
minimum values apply simultaneously to each supply.
Cumulative input level based on FM at 0 dB and NICAM at
10 dB with respect to picture carrier.
The signal amplitude present at the SEYE and CEYE pins depends on whether the demodulator is in or out-of-lock.
When out-of-lock, the signal at the pins is
√
2 times the in-lock situation.
VCO jitter is measured in System I over 100 cycles of the VCO clock.
With 10 k
resistor from I
REF
to V
SSF2
.
Audio performance is limited by the dynamic range of the NICAM 728 system. Due to compansion, the quantization
noise is never lower than
62 dB with respect to the input level.
Measured with a
30 dB, 1 kHz NICAM 728 input signal.
Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the
falling edge of SCL.
If a fast I
2
C-bus device is used in an up to 100 kbit/s I
2
C-bus system, then the requirement t
SU;DAT
≥
250 ns is always
fulfilled if this device cannot stretch the LOW level of the SCL signal. If a device stretches the LOW level of the SCL
signal, then data to SDA must be asserted (t
RD(max)
+ t
SU;DAT
) = 1000 + 250 = 1250 ns before the SCL signal is
released to be compatible with the up to 100 kbit/s I
2
C-bus specification.
2.
3.
4.
5.
6.
7.
8.
9.
Timing (all timing values refer to V
IH
and V
IL
levels)
DATAIN
WITH RESPECT TO
PCLK (see Fig.9)
t
SU;DAT
t
HD;DAT
SDA
WITH RESPECT TO
SCL(see Fig.10)
data set-up time
data hold time
100
250
ns
ns
f
SCL
t
BUF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
r
t
f
t
SU;STO
SCL clock frequency
bus free time
START code hold time
SCL clock LOW time
SCL clock HIGH time
START code set-up time
data hold time
data set-up time
SDA and SCL rise time
SDA and SCL fall time
STOP code set-up time
0
1300
600
1300
600
600
0
100
50
50
600
400
300
300
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
note 8
note 9
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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