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參數(shù)資料
| 型號： | SAA7157T-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 29 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 68K |
| 代理商： | SAA7157T-T |
May 1992
6
Philips Semiconductors
Product specication
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
CHARACTERISTICS
VDDA = 4.5 to 5.5 V; VDDD = 4.5 to 5.5 V; fLFCO = 6.0 to 7.25 MHz and Tamb = 0 to 70 °C unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
analog supply voltage (pin 5)
4.5
5.0
5.5
V
VDDD
digital supply voltage (pins 8 and 17)
4.5
5.0
5.5
V
IDDA
analog supply current (pin 5)
3
9mA
IDDD
digital supply current (I8 + I17)
note 1
10
60
mA
Vreset
power-on reset threshold voltage
Fig.4
3.5
V
Input LFCO (pin 11)
V11
DC input voltage
0
VDDA
V
Vi
input signal (peak-to-peak value)
1
VDDA
V
fLFCO
input frequency range
6.0
7.25
MHz
C11
input capacitance
10
pF
Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3
VIL
input voltage LOW
0
0.8
V
VIH
input voltage HIGH
2.0
VDDD
V
fLFCO2
input frequency range for LFCO2
6.0
7.25
MHz
ILI
input leakage current
LFCOSEL
50
150
A
others
10
A
CI
input capacitance
5pF
Output RESN (pin 12)
VOL
output voltage LOW
IO L = 2 mA
0
0.4
V
VOH
output voltage HIGH
IOH = 0.5 mA
2.4
VDDD
V
td
RESN delay time
C3 = 0.1 F; Fig.4
20
200
ms
Output CREF (pin 15)
VOL
output voltage LOW
IO L = 2 mA
0
0.6
V
VOH
output voltage HIGH
IOH = 0.5 mA
2.4
VDDD
V
fCREF
output frequency CREF
Fig.3
2 fLFCO(2)
MHz
CL
output load capacitance
15
40
pF
tSU
set-up time
Fig.3; note 1
12
ns
tHD
hold time
Fig.3; note 1
4
ns
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