
2
3
P
P
X
S
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Note
1.
X = don’t care.
Table 16
Colour look-up table and dithering configuration registers (page 10)
Table 17
Output interface configuration registers (page 11); note 1
OSDP_C3R
OSDP_C3G
OSDP_C3B
CCH W
CDH W
CEH W
00H
00H
FFH
osd_pointer_colour3_red[7:0]
osd_pointer_colour3_green[7:0]
osd_pointer_colour3_blue[7:0]
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Colour look-up table: 00H to 03H
CL_CTRL
00H
W
00 0000
write_
hsynced
quick_prog red_prog
green_prog blue_prog
cc_on
CL_INDEX
CL_VALUE_HI
CL_VALUE_LO
01H
02H
03H
W
W
W
00H
00
00H
colour_index[7:0]
colour_value[9:8]
colour_value[7:0]
Temporal dithering: 80H to 83H
DT_CTRL
80H
W
1
1
dither_
bypass
dither_colmap[1:0]
dither_
rand_mode
dither_
add_noise
dither_out_
bits
DT_COLMAP
DT_MODE
81H
82H
W
W
11
00
100
dither_
rand_mono
dither_idx_ofs_reg[2:0]
DT_NOISE
83H
W
0
0
dither_
noise_mag
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Output interface: 01H to 39H, 40H to 4AH, 51H to 59H, 61H to 6AH, 71H to 7AH, 81H to 8AH, 91H to 9AH, A1H to AAH, B1H to BAH,
C1H to CAH, D1H to DEH, E1H to EEH and F0H to F7H
000
OI_WX_LO
02H
W
02H
wait_column[7:0]
OI_INVA_DEL
03H
W
0000 0000
pin_drv_inva[2:0]
OI_INVB_DEL
04H
W
0000 0000
pin_drv_invb[2:0]
OI_PSX_HI
05H
W
000
OI_WX_HI
01H
W
wait_column[10:8]
inversion_A_pin_delay[4:0]
inversion_B_pin_delay[4:0]
picture_start_x[10:8]
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0