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參數(shù)資料
| 型號： | SAA4994H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Field and line rate converter with noise reduction |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大小： | 147K |
| 代理商： | SAA4994H |
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2001 Nov 23
6
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4994H
6
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
(1)(2)
V
SSE
YC0
YC1
YC2
YC3
YC4
YC5
YC6
YC7
UVC0
UVC1
UVC2
UVC3
REC
V
SSE
V
DDE
V
SSI
V
DDI
JUMP0
1
2
3
4
5
6
7
8
9
ground ground of output pads
input
bus C luminance input from field memory 2 bit 0 (LSB)
input
bus C luminance input from field memory 2 bit 1
input
bus C luminance input from field memory 2 bit 2
input
bus C luminance input from field memory 2 bit 3
input
bus C luminance input from field memory 2 bit 4
input
bus C luminance input from field memory 2 bit 5
input
bus C luminance input from field memory 2 bit 6
input
bus C luminance input from field memory 2 bit 7 (MSB)
input
bus C chrominance input from field memory 2 bit 0 (LSB)
input
bus C chrominance input from field memory 2 bit 1
input
bus C chrominance input from field memory 2 bit 2
input
bus C chrominance input from field memory 2 bit 3 (MSB)
output
read enable output for bus C
ground ground of output pads
supply
external supply voltage (output pads)
ground core ground
supply
core supply voltage
input
configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field
memory; should be connected to ground or to V
DDE
via a pull-up resistor of 47 k
input
configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit
1st field memory for full 4 : 2 : 2; should be connected to ground or to V
DDE
via a pull-up
resistor of 47 k
supply
external supply voltage (output pads)
supply
core supply voltage
ground core ground
input
test pin 1 input for internal RAM testing with internal pull-down; connect to ground for
normal operation
input
SNERT bus reset input
I/O
SNERT bus data input and output
input
SNERT bus clock input
ground ground of output pads
input
test pin 2 input for internal RAM testing with internal pull-down; connect to ground for
normal operation
input
test mode input with internal pull-down; if not used it has to be connected to ground
input
boundary scan test reset input (active LOW); if not used it has to be connected to V
DDE
via a pull-up resistor of 47 k
input
boundary scan test mode select input; if not used it has to be connected to V
DDE
via a
pull-up resistor of 47 k
input
boundary scan test data input; if not used it has to be connected to V
DDE
via a pull-up
resistor of 47 k
10
11
12
13
14
15
16
17
18
19
JUMP1
20
V
DDE
V
DDI
V
SSI
RAMTST1
21
22
23
24
SNRST
SNDA
SNCL
V
SSE
RAMTST2
25
26
27
28
29
TE
TRST
30
31
TMS
32
TDI
33
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