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參數(shù)資料
| 型號： | SAA4945H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | LIne MEmory noise Reduction IC LIMERIC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 116K |
| 代理商： | SAA4945H |
1997 Jun 10
9
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
Fig.4 Write enable timing.
handbook, full pagewidth
X
X
U0. 1,0
U0. 3,2
U0. 5,4
U0. 7,6
X
X
V0. 1,0
V0. 3,2
V0. 5,4
V0. 7,6
one sequence; X: non valid data
X
X
X
X
X
Y3
Y2
Y1
Y0
UI0, UI1
VI0, VI1
YI0 to YI7
WEI
(WES = 0 status register)
WEI
(WES = 1 status register)
l
X
X
U0. 1,0
U0. 3,2
U0. 5,4
U0. 7,6
X
X
V0. 1,0
V0. 3,2
V0. 5,4
V0. 7,6
one sequence; X: non valid data
X
X
X
X
X
Y3
Y2
Y1
Y0
UI0, UI1
VI0, VI1
YI0 to YI7
CLK
WEO
(WES = 0 status register)
WEO
(WES = 1 status register)
l
+
MGK172
Va (
PIN
22)
Vertical synchronization signal, active HIGH
Minimum HIGH period equals one line period
Vertical synchronization signals converted to system
clock domain internally. So the Va pulse can be
asynchronous.
See timing diagram Fig.6 and Table 11 for timing
specification.
CLK (
PIN
19)
Line locked system clock, up to 16 MHz typical
All clock related signals act on the rising edge of the
system clock.
TST0, TST1
AND
TST2 (
PINS
26, 25
AND
24)
Test mode inputs
Active HIGH, with internal pull-down resistors.
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| SAA4951 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
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