參數(shù)資料
型號(hào)： SAA16M8Yx6xV4TL
廠商： Electronic Theatre Controls, Inc.
英文描述： DOUBLE DATA RATE (DDR) SDRAM
中文描述： 雙數(shù)據(jù)速率（DDR）SDRAM內(nèi)存
文件頁(yè)數(shù)： 6/13頁(yè)
文件大?。?/td> 256K
代理商： SAA16M8YX6XV4TL
128Mb: x4, x8, x16
DDR SDRAM
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
6
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
2001, 2002, 2004 SpecTek
CAPACITANCE (x16)
(25°C < T
A
< +70°C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V)
PARAMETER
Delta Input/Output Capacitance: DQ0 – DQ7, LDQS, LDM
Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DC
IOL
DC
IOU
DC
I
1
DC
I
2
C
IO
C
I
1
C
I
2
C
I
3
MIN
--
--
--
--
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
NOTES
24
24
29
29
I
DD
SPECIFICATIONS AND CONDITIONS (x16)
(25°C < T
A
< +70°C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V)
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
t
CK =
t
CK(MIN); CKE=LOW;
IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle;
t
CK =
t
CK
(MIN); CKE = HIGH; Address and other control inputs changing once per
clock cycle. V
IN
= V
REF
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT (Part number ‘R’ only)
OPERATING CURRENT: Four bank interleaving READs (BL = 4) with
auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
RC (MIN); Address and control
inputs change only during Active, READ, or WRITE commands.
SYMBOL
I
DD
0
-75
115
-8
105
UNITS
mA
NOTES
22, 48
I
DD
1
140
115
mA
22, 48
I
DD
2
P
10
10
mA
23, 32,
50
51
I
DD
2
N
50
45
mA
I
DD
3
P
18
18
mA
23, 32,
50
22
I
DD
3
N
50
45
mA
I
DD
4
R
170
160
mA
22, 48
I
DD
4
W
150
145
mA
22
t
RC = tRFC (MIN)
I
DD
5
I
DD
7
I
DD
8
255
2
330
225
2
285
mA
mA
mA
22, 50
11
22, 49
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