參數(shù)資料
型號： SA568AD
廠商： NXP SEMICONDUCTORS
元件分類： XO, clock
英文描述： 150MHz phase-locked loop
中文描述： PHASE LOCKED LOOP, 150 MHz, PDSO20
封裝： PLASTIC, SOT-163-1, SOL-20
文件頁數(shù)： 2/9頁
文件大小： 322K
代理商： SA568AD
Philips Semiconductors
Product specification
NE/SA568A
150MHz phase-locked loop
1996 Feb 1
2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
T
J
T
STG
P
DMAX
θ
JA
PARAMETER
RATING
6
+150
-65 to +150
400
80
UNITS
V
°
C
°
C
mW
°
C/W
Supply voltage
Junction temperature
Storage temperature range
Maximum power dissipation
Thermal resistance
ELECTRICAL CHARACTERISTICS
The elctrical characteristics listed below are actual tests (unless
otherwise stated) performed on each device with an automatic IC
tester prior to shipment. Performance of the device in automated
test set-up is not necessarily optimum. The NE568A is
layout-sensitive. Evaluation of performance for correlation to the
data sheet should be done with the circuit and layout of Figures 3, 4,
and 5 with the evaluation unit soldered in place. (Do not use a
socket!)
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5V; T
A
= 25
°
C; f
O
= 70MHz, Test Circuit Figure 3, f
IN
= -20dBm, R
4
= 3.9k
, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
NE/SA568A
TYP
5
54
UNITS
MIN
4.5
MAX
5.5
70
V
CC
I
CC
Supply voltage
Supply current
V
mA
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
NE/SA568A
MIN
TYP
MAX
f
OSC
Maximum oscillator operating frequency
3
150
MHz
Input signal level
50
–20
1
2000
+10
mV
dBm
BW
Demodulated bandwidth
f
O
/7
1.0
MHz
Non-linearity
5
Dev =
±
20%, Input = -20dBm
4.0
%
Lock range
2
Input = -20dBm
±
25
±
20
±
35
±
30
% of f
O
% of f
O
ppm/
°
C
k
Capture range
2
Input = -20dBm
TC of f
O
Input resistance
4
Figure 3
100
R
IN
1
Output impedance
6
Demodulated V
OUT
Dev =
±
20% of f
O
measured at
Pin 14
0.40
0.52
V
P-P
AM rejection
V
= -20dBm (30% AM)
referred to
±
20% deviation
50
dB
f
O
Distribution
6
Centered at 70MHz, R
2
=
1.2k
, C
= 16pF, R
= 3.9k
(C
2
+ C
STRAY
= 20pF)
-15
0
+15
%
f
O
Drift with supply
4.5V to 5.5V
2
%/V
NOTE:
1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.
2. Limits are set symmetrical to f
O
. Actual characteristics may have asymmetry beyond the specified limits.
3. Not 100% tested, but guaranteed by design.
4. Input impedance depends on package and layout capacitances. See Figures 6 and 5.
5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (V
OUT
). Non-linearity is
then calculated from a straight line over the deviation range specified.
6. Free-running frequency is measured as feedthrough to Pin 14 (V
OUT
) with no input signal applied.
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