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參數(shù)資料
| 型號(hào)： | SA568A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Ceramic Multilayer Capacitor; Capacitor Type:General Purpose; Capacitance:2200pF; Capacitance Tolerance: 10%; Voltage Rating:100VDC; Capacitor Dielectric Material:Multilayer Ceramic; Package/Case:0603; Termination:SMD RoHS Compliant: Yes |
| 中文描述： | 150MHz的鎖相環(huán) |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 322K |
| 代理商： | SA568A |
Philips Semiconductors
Product specification
NE/SA568A
150MHz phase-locked loop
1996 Feb 1
4
C
9
1
2
(50) (f
O
)F
At 70MHz, the calculated value is 45pF. Empirical results with the
test and application board were improved when a 47pF capacitor
was used.
The natural frequency for the loop filter is set by C
10
and R
1
. If the
center frequency of the loop is 70MHz and the full demodulated
bandwidth is desired, i.e., f
BW
= f
O
/7 = 10MHz, and a value for R
1
is
chosen, the value of C
10
can be calculated.
C
10
1
2
R
1
f
BW
F
Also,
C
11
1
2 350 f
BW(Hz)
This capacitance determines the signal bandwidth of the output
buffer amplifier. (For further inofrmation see Philips application note
AN1881 “The NE568A Phase Locked Loop as a Wideband Video
Demodulator”.
Parts List and Layout 40MHz Application NE568AD
C
1
100nF
±
10%
Ceramic chip
C
21
18pF
±
2%
Ceramic chip
C
22
16pF
±
2%
Ceramic ORChip
C
3
100nF
±
10%
Ceramic chip
C
4
100nF
±
10%
Ceramic chip
C
5
6.8
μ
F
±
10%
Tantalum
C
6
100nF
±
10%
Ceramic chip
C
7
100nF
±
10%
Ceramic chip
C
8
100nF
±
10%
Ceramic chip
C
9
47pF
±
2%
Ceramic chip
C
10
560pF
±
2%
Ceramic chip
C
11
47pF
±
2%
Ceramic chip
C
12
100nF
±
10%
Ceramic chip
C
13
100nF
±
10%
Ceramic chip
R
1
27
±
10%
Chip CR32
R
2
1.2k
Trim pot
R
33
43
±
10%
Chip CR32
R
44
3.9k
±
10%
Chip CR32
R
53
50
±
10%
Chip CR32
RFC
15
10
μ
H
±
10%
Surface mount
RFC
25
10
μ
H
±
10%
Surface mount
NOTES:
1. 18pF with Pin 12 ground and Pin 13 no connect (open).
2. C
+ C
STRAY
= 16pF for temperature-compensated configuration
with R
4
.
3. For 50
setup. R
1
= 62
, R
3
= 75
for 75
application.
4. For test configuration R
4
= 0
(GND) and C
2
= 18pF.
5. 0
chip resistors (jumpers) may be substituted with minor degra-
dation of performance.
1206
0805
1206
1206
35V
1206
1206
1206
0805 or 1206
0805 or 1206
0805 or 1206
1206
1206
1/4W
1/4W
1/4W
1/4W
Parts List and Layout 70MHz Application NE568AN
C
1
100nF
±
10%
Ceramic chip
C
21
18pF
±
2%
Ceramic chip
C
22
16pF
±
2%
Ceramic chip
C
3
100nF
±
10%
Ceramic chip
C
4
100nF
±
10%
Ceramic chip
C
5
6.8
μ
F
±
10%
Tantalum
C
6
100nF
±
10%
Ceramic chip
C
7
100nF
±
10%
Ceramic chip
C
8
100nF
±
10%
Ceramic chip
C
9
47pF
±
2%
Ceramic chip
C
10
560pF
±
2%
Ceramic chip
C
11
47pF
±
2%
Ceramic chip
C
12
100nF
±
10%
Ceramic chip
C
13
100nF
±
10%
Ceramic chip
R
1
27
±
10%
Ceramic
CR32
R
2
1.2k
Trim pot
R
33
43
±
10%
Ceramic
CR32
R
44
3.9k
±
10%
Ceramic
CR32
R
53
50
±
10%
Ceramic
CR32
RFC
1
10
μ
H
±
10%
Surface mount
RFC
2
10
μ
H
±
10%
Surface mount
50V
50V
0805
50V
50V
35V
50V
50V
50V
50V
50V
50V
50V
50V
1/4W
chip
chip
1/4W
chip
1/4W
chip
1/4W
NOTES:
1. 18pF with Pin 12 ground and Pin 13 no connect (open).
2. C
2
+ C
STRAY
= 16pF for temperature-compensated configuration
with R
4
= 3.9k
.
3. For 50
setup. R
= 62
, R
3
= 75
for 75
application.
4. For test configuration R
4
= 0
(GND) and C
2
= 18pF.
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