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參數(shù)資料
| 型號： | SA25F020LENF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 14/37頁 |
| 文件大小： | 560K |
| 代理商： | SA25F020LENF |
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SA25F020 Advanced Information
SAIFUN
14
Serial Interface
Description
SPI Modes
These devices can be driven by a
microcontroller with its SPI peripheral
running in either of the two following
modes:
=
=
CPOL=0, CPHA=0
CPOL=1, CPHA=1
In both of these modes, input data is
latched on the rising edge of SCK, and
output data is available from the falling
edge of SCK. The difference between the
two modes, as shown in Figure 7, is the
clock polarity when the bus master is in
Standby mode and is not transferring data,
as follows:
=
SCK remains at 0 for CPOL = 0,
CPHA = 0
=
SCK remains at 1 for CPOL = 1,
CPHA = 1
MSB
MSB
CS
CS
SO
SI
0
1
0
1
CPOL
CPHA
Figure 7. Supported SPI Modes
Master
The device that generates the SCK.
Slave
As the SCK pin is always an input, the
SA25F020 always operates as a slave.
Transmitter/Receiver
The
designated for data transmission and
reception.
SA25F020
has
separate
pins
Serial Opcode
The first byte is received after the device is
selected. This byte contains the opcode
that defines the operation to be performed
(for more details, refer to Table 6,
page 17).
Invalid Opcode
If an invalid opcode is received, no data is
shifted into the SA25F020, and the serial
output pin remains in a high impedance
state until a CSb falling edge is detected
again,
which
reinitializes
communication.
the
serial
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相關(guān)代理商/技術(shù)參數(shù) |
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