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參數(shù)資料
| 型號(hào)： | SA1620BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Low voltage GSM front-end transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 203K |
| 代理商： | SA1620BE |
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Philips Semiconductors
Product specification
SA1620
Low voltage GSM front-end transceiver
1997 May 22
10
Table 3.
Power-Down and Tx/Rx Control Logic
No.
PONBUF
PDTX
PONRX
MODE
RESULT
1
H
H
L
Standby
LO buffer active, Tx and Rx path inactive
2
H
L
L
Transmit
LO buffer active, Tx path active, Rx path inactive (LNAs + mixer)
3
H
H
H
Receive
Tx path inactive, LO buffer and Rx path active (LNAs + mixer)
4
H
L
H
Calibrate
Tx path and Rx LNAs inactive, LO buffer and Rx mixer active
5
L
x
x
Power-Down
Tx- and Rx-path, LO buffers and Bias inactive
NOTES:
1. Logic levels of PONBUF, PDTx and PONRx: TTL, see DC Electrical Characteristics.
2. Logic levels / polarities are compatible with Philips Semiconductors Power Amp Controller PCA5075 and synthesizers UMA1019 or SA8025.
3. First stage of LO buffer and parts of bias supply are powered on by PONBUF.
4. Tx- or Rx-paths may be activated for special timeslots. Lines 1 and 4 show options to support DC offset calibrations at baseband mixers,
following in the receiver chain (SA1638).
Table 4.
Gain Control Logic for LNA1 and LNA2
INPUT
ATTENUATION
STEP
GAIN
POWER CONSUMPTION
a
b
LNA1
LNA2
LNA1
LNA2
H
H
0
G1hi
G2hi
on
on
H
L
1
G1hi
G2lo1
on
off
L
H
2
G1hi
G2lo2
on
off
L
L
3
G1lo
G2lo3
off
off
NOTES:
1. Logic levels of a and b: TTL
2. For values of G1hi and G1lo, G2hi, G2lo1, G2lo2 and G2lo3 see LNA1 and LNA2 AC Electrical Characteristics.
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