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參數(shù)資料
| 型號： | SA1620 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage GSM front-end transceiver(低壓GSM前端收發(fā)器) |
| 中文描述： | 低電壓的GSM前端收發(fā)器（低壓手機前端收發(fā)器） |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 203K |
| 代理商： | SA1620 |
Philips Semiconductors
Product specification
SA1620
Low voltage GSM front-end transceiver
1997 May 22
9
AC ELECTRICAL CHARACTERISTICS
(continued)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
1
TYP
UNITS
MIN
1
-3
σ
3
σ
MAX
1
Rx Mixer
PG
C
Power conversion gain
5
7.5
+8.5
9.5
dB
RF = 1800MHz
–4
S
11
Mixer input match at ports INM
and INMX
4
SSB combined noise figure
–13
dB
NF
M
P
-1dB
IIP3
IIP3/
t
IIP2
10
dB
Input 1dB compression
–7.3
dBm
Input third order intercept
0
2
4
dBm
dB/
°
C
dBm
Input third order intercept
0.005
Input second order intercept
19
G
RFM-IF
G
LOfloor
G
LO-IF
G
LO-RFM
RF feedthrough
400MHz
–26
dB
LO floor feedthrough
400MHz
–30
dB
LO feedthrough to IF
1.3GHz
–16
dB
LO to mixer input feedthrough
1.3GHz
–50
dBm
G
LO-RF1
LO to RF LNA1 input
feedthrough
LNA1 output to LNA2 input
feedthrough
LNA2 output to mixer input
feedthrough
LNA1 output to mixer input
feedthrough
1.3GHz
–65
dBm
G
LNA1-2
400MHz
1290-1760MHz
–41
–26
dB
G
LNA2-M
1290-1760MHz
–23
dB
G
LNA1-M
400MHz
1290-1760MHz
–50
–35
dB
Receiver
6
Cascaded gain
A,B Logic Level
H,H
23.5
26.5
28.5
30.5
33.5
dB
H,L
6
9
11
13
16
dB
L,H
–8
–5
–3
–1
+2
dB
L,L
–41
–36
–32
+28
–23
dB
Input IP3 @ RFin=–40dBm
H,H
–20
–18
–16
dBm
LO input
Z
IN
Input impedance
(each single-ended input)
Input power
1.3GHz
35-j97
P
IN
–25
7
–15
dBm
A
SAT
Transistor saturation limit,
max input amplitude
500
mV
Tx IF input
|Z
IN
|
P
IN
Tx RF output
Input impedance
400MHz
2
k
dBm
Input power
–20
P
OUT
R546 = 240
,
V
CC
Tx1,2 = 3V
5
7.5
8.5
9.5
dBm
NOTES:
1. Due to our automatic test equipment accuracy and repeatability test limits may not reflect the ultimate device performance. Standard
deviations are calculated from characterization data.
2. If the LNA1 is not needed, connect pin V
L1 and IN1 to GND. If the LNA2 is not needed, connect pin V
CC
L2 and IN2 to GND.
3. Simple L/C elements are needed to achieve specified return loss.
4. The mixer RF inputs (emitters of a Gilbert Cell) may be driven by a symmetrical matching network.
5. Input symmetry suppression is such that the product 6*RF–4*LO is to be suppressed by at least 66dB relative to the wanted IF output when
the input to the mixer is at –32dBm.
6. LNA1, LNA2, and the mixer are cascaded. 0 db insertion loss between LNA1 out to LNA2 in and LNA2 out to mixer in.
7. Lowering the LO input power (P
IN
) from TYP to MIN will lower the mixer gain (PG
C
) by 1 dB.
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