
Chapter 11 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XDP512 Data Sheet, Rev. 2.13
Freescale Semiconductor
517
NOTE
Writing to these registers when in special modes can alter the PWM
functionality.
11.3.2.12 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.
The counter can be read at any time without affecting the count or the operation of the PWM channel. In
left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned
output mode, the counter counts from 0 up to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. The counter is also cleared at the end of the effective period (see
details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the
PWMCNTx register. For more detailed information on the operation of the counters, see
Section 11.4.2.4,In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
NOTE
Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.
Read: Anytime
Write: Anytime (any value written causes PWM counter to be reset to $00).
11.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
76543210
R
Bit 7
6
5
4
3
2
1
Bit 0
W
00000000
Reset
00000000
Figure 11-14. PWM Channel Counter Registers (PWMCNTx)