參數(shù)資料
型號(hào): S71GL064A08BAW0F2
廠商: SPANSION LLC
元件分類(lèi): 存儲(chǔ)器
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA56
封裝: 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56
文件頁(yè)數(shù): 85/102頁(yè)
文件大小: 1606K
代理商: S71GL064A08BAW0F2
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
85
A d v a n c e I n f o r m a t i o n
Switching Waveforms
Notes:
1.
To achieve 55-ns performance, the read access should be CE# controlled. In this case t
ACE
is the critical parameter and t
SK
is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Device is continuously selected. OE#, CE# = V
IL
.
2.
3.
WE# is High for Read Cycle.
Notes:
1.
To achieve 55-ns performance, the read access should be CE# controlled. In this case t
ACE
is the critical parameter and t
SK
is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
WE# is High for Read Cycle.
2.
Figure 26. Read Cycle 1 (Address Transition Controlled)
Figure 27. Read Cycle 2 (OE# Controlled)
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
tAA
tOHA
t
SK
DATA VALID
t
RC
t
ACE
t
DOE
t
t
LZCE
HIGH IMPEDENCE
t
HZOE
HIGH
IMPEDENCE
ADDRESS
CE
2
t
HZBE
t
LZBE
t
HZCE
DATA OUT
t
DBE
t
SK
CE#1
BHE#/BLE#
OE#
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