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參數(shù)資料
| 型號(hào)： | S568013MFA00E |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁(yè)數(shù)： | 109/125頁(yè) |
| 文件大?。?/td> | 1702K |
| 代理商： | S568013MFA00E |
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56F8013/56F8011 Data Sheet, Rev. 11
84
Freescale Semiconductor
Figure 6-16 Timing Relationships of Reset Signal to Clocks
6.8 Interrupts
The SIM generates no interrupts.
Part 7 Security Features
The 56F8013/56F8011 offer security features intended to prevent unauthorized users from reading the
contents of the Flash Memory (FM) array. The 56F8013/56F8011’s Flash security consists of several
hardware interlocks that prevent unauthorized users from gaining access to the Flash array.
Note, however, that part of the security must lie with the user’s code. An extreme example would be user’s
code that includes a subroutine to read and transfer the contents of the internal program to SCI, SPI or
another peripheral, as this code would defeat the purpose of security. At the same time, the user may also
wish to put a “backdoor” in his program. As an example, the user downloads a security key through the
SCI, allowing access to a programming routine that updates parameters stored in another section of the
Flash.
RST
MSTR_OSC
CKGEN_RST
SYS_CLK_x2
SYS_CLK
SYS_CLK_D
SYS_CLK_DIV2
PERIP_RST
CORE_RST
Switch on falling OSC_CLK
96 MSTR_OSC cycles
Switch on falling SYS_CLK
32 SYS_CLK cycles delay
Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles
for combined reset extension
Switch on falling SYS_CLK
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