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NMOS linear image sensor
S3901/S3904 series
I
Driver circuit
S3901/S3904 series do not require any DC voltage supply
for operation. However, the Vss, Vsub and all NC terminals
must be grounded. A start pulse
φ
st and 2-phase clock pulses
φ
1,
φ
2 are needed to drive the shift register. These start and
clock pulses are positive going pulses and CMOS logic com-
patible.
The 2-phase clock pulses
φ
1,
φ
2 can be either completely
separated or complementary. However, both pulses must not
be
“
High
”
at the same time.
A clock pulse space (X1 and X2 in Figure 7) of a
“
rise time/fall
time - 20
”
ns or more should be input if the rise and fall times
of
φ
1,
φ
2 are longer than 20 ns. The
φ
1 and
φ
2 clock pulses
must be held at
“
High
”
at least 200 ns. Since the photodiode
signal is obtained at the rise of each
φ
2 pulse, the clock pulse
frequency will equal the video data rate.
The amplitude of start pulse
φ
st is the same as the
φ
1 and
φ
2
pulses. The shift register starts the scanning at the
“
High
”
level of
φ
st, so the start pulse interval determines the length of
signal accumulation time. The
φ
st pulse must be held
“
High
”
at least 200 ns and overlap with
φ
2 at least for 200 ns. To
operate the shift register correctly,
φ
2 must change from the
“
High
”
level to the
“
Low
”
level only once during
“
High
”
level of
φ
st. The timing chart for each pulse is shown in Figure 7.
I
End of scan
The end of scan (EOS) signal appears in synchronization
with the
φ
2 timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
k
resistor.
tvd
tpw
1
tpw
2
tpw
s
st
V
s (H)
V
s (L)
V
1 (H)
V
1 (L)
V
2 (H)
V
2 (L)
1
2
END OF SCAN
st
1
2
tr
s
tf
s
tr
1
tf
1
X1
X2
t
ov
tf
2
tr
2
ACTIVE VIDEO OUTPUT
KMPDC0022EA
Figure 7 Timing chart for driver circuit
I
Signal readout circuit
There are two methods for reading out the signal from an NMOS
linear image sensor. One is a current detection method using
the load resistance and the other is a current integration method
using a charge amplifier. In either readout method, a positive
bias must be applied to the video line because photodiode
anodes of NMOS linear image sensors are set at 0 V (Vss).
Figure 8 shows a typical video bias voltage margin. As the clock
pulse amplitude is higher, the video bias voltage can be set
larger so the saturation charge can be increased. The rise and
fall times of the video output waveform can be shortened if the
video bias voltage is reduced while the clock pulse amplitude is
still higher. When the amplitude of
φ
1,
φ
2 and
φ
st is 5 V, setting
the video bias voltage at 2 V is recommended.
To obtain good linearity, using the current integration method is
advised. In this method, the integration capacitance is reset to
the reference voltage level immediately before each photodiode
is addressed and the signal charge is then stored as an integra-
tion capacitive charge when the address switch turns on. Fig-
ures 9 and 10 show a typical current integration circuit and its
pulse timing chart. To ensure stable output, the rise of a reset
pulse must be delayed at least 50 ns from the fall of
φ
2.
Hamamatsu provides the following driver circuits and related
products (sold separately).
KMPDB0043EA
Figure 8 Video bias voltage margin
4
0
6
8
10
4
5
6
7
8
10
CLOCK PULSE AMPLITUDE (V)
V
2
9
MIN.
VIDEO BIAS RANGE
MAX
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