
NMOS linear image sensor
S3901-1024Q, S3904-2048Q
Figure 3 Dimensional outline (unit: mm)
KMPDC0109EA
Figure 4 Pin connection
KMPDA0123EA
25.6 ± 0.5
7
7
1
65.0
0.25
15.24
1
3
PHOTOSENSITIVE
SURFACE
* Optical distance from the outer surface
of the quartz window to the chip surface
2.54
0.46
25.4
48.26
ACTIVE AREA
51.2 × 2.5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
END OF SCAN
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
2
1
st
Vss
Vscg
NC
Vscd
Vss
ACTIVE VIDEO
DUMMY VIDEO
Vsub
Vss, Vsub and NC should be grounded.
Terminal
Input or output
Description
φ
1,
φ
2
Input
(CMOS logic compatible)
Pulses for operating the MOS shift register. The video data rate is
equal to the clock pulse frequency since the video output signal is
obtained synchronously with the rise of
φ
2 pulse.
Pulse for starting the MOS shift register operation. The time interval
between start pulses is equal to the signal accumulation time.
Connected to the anode of each photodiode. This should be
grounded.
Used for restricting blooming. This should be grounded.
Used for restricting blooming. This should be biased at a voltage
equal to the video bias voltage.
Video output signal. Connects to photodiode cathodes when the
address is on. A positive voltage should be applied to the video
line in order to use photodiodes with a reverse voltage. When the
amplitude of
φ
1 and
φ
2 is 5 V, a video bias voltage of 2 V is
recommended.
This has the same structure as the active video, but is not
connected to photodiodes, so only spike noise is output. This
should be biased at a voltage equal to the active video or left as an
open-circuit when not needed.
Connected to the silicon substrate. This should be grounded.
This should be pulled up at 5 V by using a 10 k
resistor. This is a
negative going pulse that appears synchronously with the
φ
2
timing right after the last photodiode is addressed.
Should be grounded.
φ
st
Input
(CMOS logic compatible)
Vss
-
Vscg
Input
Vscd
Input
Active video
Output
Dummy video
Output
Vsub
-
End of scan
Output
(CMOS logic compatible)
NC
-
3