參數(shù)資料
型號: S29WS256N0PBAW011
廠商: Spansion Inc.
英文描述: 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述: 256/128/64兆位的CMOS 1.8伏只有同時讀/寫突發(fā)模式閃存
文件頁數(shù): 18/99頁
文件大?。?/td> 1091K
代理商: S29WS256N0PBAW011
January 25, 2005 S29WS-N_00_G0
23
Ad vance
Information
Table 7.6. Address/Boundary Crossing Latency (S29WS128N/S29WS064N)
Figure 7.2. Synchronous Read
7.3.3 Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addressable
memory location. The burst read mode continues until the system drives CE# high, or RESET=
Word
Wait States
Cycle
0
5, 6, 7 ws
D0
D1
D2
D3
1 ws
D4
D5
D6
D7
1
5, 6, 7 ws
D1
D2
D3
1 ws
D4
D5
D6
D7
2
5, 6, 7 ws
D2
D3
1 ws
D4
D5
D6
D7
3
5, 6, 7 ws
D3
1 ws
D4
D5
D6
D7
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Load Initial Address
Address = RA
Read Initial Data
RD = DQ[15:0]
Read Next Data
RD = DQ[15:0]
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
End of Data?
Yes
Crossing
Boundary?
No
Yes
Completed
Delay X Clocks
Unlock Cycle 1
Unlock Cycle 2
RA = Read Address
RD = Read Data
Command Cycle
CR = Configuration Register Bits CR15-CR0
Note: Setup Configuration Register parameters
No
Refer to the Latency tables.
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