參數(shù)資料
型號: S29PL129N65GAWW03
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述: 8M X 16 FLASH 3V PROM, 65 ns, PBGA64
封裝: 8 X 11.60 MM, LEAD FREE, FBGA-84
文件頁數(shù): 10/74頁
文件大?。?/td> 1968K
代理商: S29PL129N65GAWW03
10
S29PL-N MirrorBit
Flash Family
S29PL-N_00_A5 June 6, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
2.
Input/Output Descriptions and Logic Symbols
Table 2.1
identifies the input and output package connections provided on the device.
Figure 2.1
Logic Symbols – PL256N, PL129N, and PL127N
Table 2.1
Input/Output Descriptions
Symbol
Type
Description
A
max
– A0
Input
Address bus
DQ15 – DQ0
I/O
16-bit data inputs/outputs/float
CE#
Input
Chip Enable input
OE#
Input
Output Enable input
WE#
Input
Write Enable
V
SS
Supply
Device ground
NC
Not connected
Pin Not Connected Internally
RY/BY#
Output
Ready/Busy output and open drain.
When RY/BY#= V
IH
, the device is ready to accept read operations and commands.
When RY/BY#= V
, the device is either executing an embedded algorithm or the device is
executing a hardware reset operation.
V
CC
Supply
Device Power Supply
RESET#
Input
Hardware reset pin
CE1#, CE2#
Input
Chip Enable inputs for S29PL129 device
Logic Symbol – PL256N and PL127N
Logic Symbol – PL129N
Note
1. Amax = 23 for the PL256N and 22 for the PL127N.
m
a
x +1
16
Am
a
x –A0
WP#/ACC
RE
S
ET#
CE#
OE#
WE#
RY/BY#
DQ15 – DQ0
VCC
22
16
DQ15 – DQ0
A21 – A0
WP#/ACC
RE
S
ET#
CE1#
OE#
WE#
RY/BY#
CE2#
VCC
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