參數(shù)資料
型號(hào): S29PL127N
廠商: Spansion Inc.
英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述: 256/128/128字節(jié)(16/8/8 M中的x 16位),3.0伏的CMOS只同步讀/寫(xiě),頁(yè)模式閃存
文件頁(yè)數(shù): 20/74頁(yè)
文件大?。?/td> 1968K
代理商: S29PL127N
20
S29PL-N MirrorBit
Flash Family
S29PL-N_00_A5 June 6, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
7.
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset features of
the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns
into the command registers (see
Table 12.1 on page 66
and
Table 12.2 on page 68
). The command register
itself does not occupy any addressable memory location. Instead, the command register is composed of
latches that store the commands, along with the address and data information needed to execute the
command. The contents of the register serve as input to the internal state machine and the state machine
outputs dictate the function of the device. Writing incorrect address and data values or writing them in an
improper sequence can place the device in an unknown state, in which case the system must write the reset
command to return the device to the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation.
Table 7.1
describes the required state of each
control pin for any particular operation.
Legend
L = Logic Low = V
IL
V
HH
= 8.5 – 9.5 V
SA = Sector Address
D
IN
= Data In
H = Logic High = V
IH
X = Don’t Care
A
IN
= Address In
D
OUT
= Data Out
Note
WP#/ACC must be high when writing to upper two and lower two sectors (PL256N: 0, 1,132, and 133; PL127/129N: 0, 1, 68, and 69)
Table 7.1
Device Operation
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A
max
– A0)
A
IN
DQ15 – DQ0
Read
L
L
H
H
X
D
OUT
Write
L
H
L
H
X
(See Note)
A
IN
D
IN
Standby
H
X
X
H
X
A
IN
High-Z
Output Disable
L
H
H
H
X
A
IN
High-Z
Reset
X
X
X
L
X
A
IN
High-Z
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