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| 型號： | S29NS512PABBJW000 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64 |
| 封裝： | 8 X 9.20 MM, LEAD FREE, TFBGA-64 |
| 文件頁數(shù)： | 44/86頁 |
| 文件大?。?/td> | 2234K |
| 代理商： | S29NS512PABBJW000 |
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44
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low
Level Driver User’s Guide
(
www.spansion.com
) for general information on Spansion Flash memory software
development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
The following is a C source code example of using the program resume function. Refer to the
Spansion Low
Level Driver User’s Guide
(
www.spansion.com
) for general information on Spansion Flash memory software
development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
6.5.7
Accelerated Program/Sector Erase
Accelerated single word programming, write buffer programming and sector erase, operations are enabled
through the V
PP
function. This method is faster than the standard chip program and erase command
sequences.
The accelerated chip program and erase functions must not be used more than 100 times per sector.
In addition, accelerated chip program and erase should be performed at room temperature
(30°C
±
10°C).
If the system asserts V
HH
on this input, the device automatically enters the accelerated mode and uses the
higher voltage on the input to reduce the time required for program and erase operations. The system can
then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a
Write-to-Buffer-Abort Reset
is required while in Unlock Bypass mode, the full 3-cycle RESET command
sequence must be used to reset the device. Removing V
HH
from the V
PP
input, upon completion of the
embedded program or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising V
PP
to V
HH
.
The V
PP
pin must not be at V
HH
for operations other than accelerated programming and accelerated sector
erase, or device damage may result.
The V
PP
pin must not be left floating or unconnected; inconsistent behavior of the device may result.
V
PP
locks all sector if set to V
IL
; V
PP
should be set to V
IH
for all other conditions.
6.5.8
Unlock Bypass
The unlock bypass feature allows the system to primarily program to a bank faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then
enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. The host system may also initiate the chip
erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four
cycles in length instead of six cycles.
Table 11.1
shows the requirements for the unlock bypass command
sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase,
Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode,
the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain
Table 6.22
Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0030h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS512PABBJW003 | MirrorBit Flash Family |
| S29NS-P | MirrorBit Flash Family |
| S29PL127N65GFWW02 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL127N | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL129N65GAWW02 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS512PABBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS-J | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
| S29NS-J_07 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
| S29NS-N | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS-N_07 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
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