參數(shù)資料
型號: S29GL128P10TAI012
廠商: Spansion Inc.
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述: 3.0伏只頁面模式閃存具有90納米MirrorBit工藝技術
文件頁數(shù): 11/77頁
文件大?。?/td> 2121K
代理商: S29GL128P10TAI012
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit
Flash Family
11
D a t a
S h e e t
( P r e l i m i n a r y )
2.
Input/Output Descriptions & Logic Symbol
Table 2.1
identifies the input and output package connections provided on the device.
Table 2.1
Input/Output Descriptions
Symbol
Type
Description
A25–A0
Input
Address lines for GL01GP
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
DQ14–DQ0
I/O
Data input/output.
DQ15/A-1
I/O
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
CE#
Input
Chip Enable.
OE#
Input
Output Enable.
WE#
Input
Write Enable.
V
CC
V
IO
V
SS
NC
Supply
Device Power Supply.
Supply
Versatile IO Input.
Supply
Ground.
No Connect
Not connected internally.
RY/BY#
Output
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
V
IL
, the device is actively erasing or programming. At High Z, the device is in ready.
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-
DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in
word configuration and data I/O pins DQ0-DQ15 are active.
BYTE#
Input
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#/ACC
Input
Write Protect/Acceleration Input. At V
IL
, disables program and erase functions in the
outermost sectors. At V
HH
, accelerates programming; automatically places device in
unlock bypass mode. Should be at V
IH
for all other conditions. WP# has an internal pull-
up; when unconnected, WP# is at V
IH
.
Reserved for future use.
RFU
Reserved
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