參數(shù)資料
型號: S29GL128M90TDIR22
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
中文描述: 8M X 16 FLASH 3V PROM, 90 ns, PDSO56
封裝: LEAD FREE, TSOP-56
文件頁數(shù): 99/160頁
文件大?。?/td> 2142K
代理商: S29GL128M90TDIR22
April 30, 2004 S29GLxxxM_00A5
S29GLxxxM MirrorBit
TM
Flash Family
99
P r e l i m i n a r y
Table 27. CFI Query Identification String
Table 28. System Interface String
Note:
CFI data related to V
CC
and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering
Information tables to obtain the V
CC
range for particular part numbers. Please contact the Erase and Programming Performance
table for typical timeout specifications.
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Addresses
(x16)
Addresses
(x8)
Data
Description
1Bh
36h
0027h
V
CC
Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0036h
V
CC
Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh
3Ch
0000h
V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh
3Eh
0007h
Reserved for future use
20h
40h
0007h
Typical timeout for Min. size buffer write 2
N
μ
s (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2
N
ms
22h
44h
0000h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
46h
0001h
Reserved for future use
24h
48h
0005h
Max. timeout for buffer write 2
N
times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2
N
times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
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