參數(shù)資料
型號(hào)： S29GL064N11BFI040
廠商： Spansion Inc.
英文描述： 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
中文描述： 64兆，32兆位3.0伏只頁(yè)面模式閃存具有110納米MirrorBit工藝技術(shù)
文件頁(yè)數(shù)： 17/79頁(yè)
文件大小： 2191K
代理商： S29GL064N11BFI040
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit
Flash Family
17
D a t a
S h e e t
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device.
Table 8.1
lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
V
ID
= 11.5–12.5
V
V
HH
= 11.5–12.5
V
X = Don’t Care
SA = Sector Address
A
IN
= Address In
D
IN
= Data In
D
OUT
= Data Out
Notes
1. If WP# = V
IL
, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot sector devices). If WP#
= VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method described in Write Protect (WP#). All
sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
2. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see
Figure 10.5 on page 56
).
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic
1
, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic
0
, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
IH
.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See
Reading Array Data
on page 41
for more information. Refer to the AC Read-Only Operations table for
timing specifications and the timing diagram. Refer to the DC Characteristics table for the active current
specification on reading array data.
Table 8.1
Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#
ACC
Addresses
DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
D
OUT
(Note 2)
BYTE#
= V
IL
Read
L
L
H
H
X
X
A
IN
A
IN
A
IN
X
D
OUT
(Note 2)
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
L
H
L
H
(Note 1)
X
Accelerated Program
L
H
L
H
(Note 1)
V
HH
H
(Note 2)
(Note 2)
Standby
V
CC
±
0.3V
L
X
X
V
CC
±
0.3V
H
X
High-Z
High-Z
High-Z
Output Disable
H
H
X
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
X
High-Z
High-Z
High-Z
相關(guān)PDF資料
PDF描述
S29GL064N11BFI042 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BFI060 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BFI062 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BFI070 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BFI072 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
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