參數(shù)資料
型號: S29GL032M10BFIR40
廠商: SPANSION LLC
元件分類: PROM
英文描述: MirrorBit Flash Family
中文描述: 2M X 16 FLASH 3V PROM, 100 ns, PBGA48
封裝: 8 X 9 MM, LEAD FREE, FBGA-48
文件頁數(shù): 89/116頁
文件大?。?/td> 6024K
代理商: S29GL032M10BFIR40
72
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
Data
Sheet
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any
sector address within the sector being erased. During chip erase, a valid address is any
non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 can change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algo-
rithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE#
pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can
be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes program-
ming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode,
the standby mode, or in the erase-suspend-read mode. Table 36 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at
any address, and is valid after the rising edge of the final WE# pulse in the command sequence
(prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles.
When the operation is complete, DQ6 stops toggling.
DQ7 = Data?
Yes
No
DQ5 = 1?
No
Yes
FAIL
PASS
Read DQ15–DQ0
Addr = VA
Read DQ15–DQ0
Addr = VA
DQ7 = Data?
START
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