參數(shù)資料
型號(hào): S29GL032A30FAIR20
廠商: Spansion Inc.
英文描述: 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology
中文描述: 64兆,32兆和16兆位3.0伏只頁(yè)面模式閃存,含有200納米MirrorBit工藝技術(shù)
文件頁(yè)數(shù): 65/95頁(yè)
文件大小: 2389K
代理商: S29GL032A30FAIR20
September 10, 2007 S29GL-A_00_A11
S29GL-A
65
D a t a
S h e e t
10.6
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 μs, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see
DQ7: Data# Polling
on page 63
).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 10.2 on page 68
shows the outputs for Toggle Bit I on DQ6.
Figure 10.4 on page 66
shows the toggle
bit algorithm.
Figure 16.9 on page 81
shows the toggle bit timing diagrams.
Figure 16.10 on page 81
shows
the differences between DQ2 and DQ6 in graphical form. See
DQ2: Toggle Bit II
on page 66
.
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