- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385794 > S29GL032A30BFI013 (Spansion Inc.) 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology PDF資料下載
參數(shù)資料
| 型號： | S29GL032A30BFI013 |
| 廠商： | Spansion Inc. |
| 英文描述： | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| 中文描述： | 64兆，32兆和16兆位3.0伏只頁面模式閃存，含有200納米MirrorBit工藝技術(shù) |
| 文件頁數(shù)： | 59/95頁 |
| 文件大?。?/td> | 2389K |
| 代理商： | S29GL032A30BFI013 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁
September 10, 2007 S29GL-A_00_A11
S29GL-A
59
D a t a
S h e e t
10. Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command.
Table 10.2 on page 61
and
Table 10.1 on page 62
shows the address and data requirements for the sector erase command sequence.
The device does
not
require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 μs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 μs, otherwise erasure may begin. Any sector erase address and
command following the exceeded time-out may or may not be accepted. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written.
Any command other than Sector Erase or
Erase Suspend during the time-out period resets the device to the read mode.
Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress.
The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See
DQ3: Sector Erase
Timer
on page 67
). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to
Write Operation Status
on page 63
for information on these status bits.
Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are
ignored. However, note that a
hardware reset
immediately
terminates the erase operation. If that occurs, the
sector erase command sequence should be reinitiated once the device returns to reading array data, to
ensure data integrity.
Figure 10.1
illustrates the algorithm for the erase operation. Refer to
Table 16.5 on page 76
for parameters,
and
Figure 16.7 on page 80
for timing diagrams.
Figure 10.1
Erase Operation
Notes
1. See
Table 10.2 on page 61
and
Table 10.1 on page 62
for program command sequence.
2. See
DQ3: Sector Erase Timer on page 67
for information on the sector erase timer.
S
TART
Write Er
as
e
Comm
a
nd
S
e
qu
ence
(Note
s
1, 2)
D
a
t
a
Poll to Er
as
ing
B
a
nk from
S
y
s
tem
D
a
t
a
= FFh
No
Ye
s
Er
asu
re Completed
Em
b
edded
Er
as
e
a
lgorithm
in progre
ss
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29GL032A30BFIR10 | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR12 | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR13 | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR20 | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR22 | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL032A30BFIR10 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR12 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR13 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR20 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL032A30BFIR22 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。