參數(shù)資料
型號: S29GL032A100TFIR10
廠商: Spansion Inc.
英文描述: 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology
中文描述: 64兆,32兆和16兆位3.0伏只頁面模式閃存,含有200納米MirrorBit工藝技術(shù)
文件頁數(shù): 63/95頁
文件大小: 2389K
代理商: S29GL032A100TFIR10
September 10, 2007 S29GL-A_00_A11
S29GL-A
63
D a t a
S h e e t
10.3
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7.
Table 10.2 on page 68
and the following subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an
Embedded Program or Erase operation is in progress or is completed.
10.4
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 μs, then the device returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a
0
on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a
1
on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 μs, then the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
the status or valid data. Even if the device completed the program or erase operation and DQ7 has valid data,
the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 appears on successive read
cycles.
Table 10.2 on page 68
shows the outputs for Data# Polling on DQ7.
Figure 10.3 on page 64
shows the Data#
Polling algorithm.
Figure 16.8 on page 80
shows the Data# Polling timing diagram.
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S29GL032A100TFIR20 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology
S29GL032A100TFIR22 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology
S29GL032A100TFIR23 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology