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    參數(shù)資料
    型號: S29AL016M90FAI012
    廠商: SPANSION LLC
    元件分類: DRAM
    英文描述: Hex Schmitt Trigger; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
    中文描述: 1M X 16 FLASH 3V PROM, 90 ns, PBGA64
    封裝: 13 X 11 MM, FBGA-64
    文件頁數(shù): 27/59頁
    文件大?。?/td> 1917K
    代理商: S29AL016M90FAI012
    April 21, 2004 S29AL016M_00A4
    S29AL016M
    28
    Figure 5
    illustrates the algorithm for the erase operation. See the
    Erase/Program
    Operations
    tables in
    “AC Characteristics”
    for parameters, and to
    Figure 18
    for tim-
    ing diagrams.
    Sector Erase Command Sequence
    Sector erase is a six bus cycle operation. The sector erase command sequence is
    initiated by writing two unlock cycles, followed by a set-up command. Two addi-
    tional unlock write cycles are then followed by the address of the sector to be
    erased, and the sector erase command. Tables
    10
    11
    show the address and data
    requirements for the sector erase command sequence.
    Note that the SecSi Sec-
    tor, autoselect, and CFI functions are unavailable when an erase operation is
    in progress.
    The device does
    not
    require the system to preprogram the memory prior to erase.
    The Embedded Erase algorithm automatically programs and verifies the sector for
    an all zero data pattern prior to electrical erase. The system is not required to
    provide any controls or timings during these operations.
    After the command sequence is written, a sector erase time-out of 50 μs begins.
    During the time-out period, additional sector addresses and sector erase com-
    mands may be written. Loading the sector erase buffer may be done in any
    sequence, and the number of sectors may be from one sector to all sectors. The
    time between these additional cycles must be less than 50 μs, otherwise the last
    address and command might not be accepted, and erasure may begin. It is rec-
    ommended that processor interrupts be disabled during this time to ensure all
    commands are accepted. The interrupts can be re-enabled after the last Sector
    Erase command is written. If the time between additional sector erase commands
    can be assumed to be less than 50 μs, the system need not monitor DQ3.
    Any
    command other than Sector Erase or Erase Suspend during the time-out
    period resets the device to reading array data.
    The system must rewrite the
    command sequence and any additional sector addresses and commands.
    The system can monitor DQ3 to determine if the sector erase timer has timed
    out. (See the
    “DQ3: Sector Erase Timer”
    section.) The time-out begins from the
    rising edge of the final WE# pulse in the command sequence.
    Once the sector erase operation has begun, only the Erase Suspend command is
    valid. All other commands are ignored. Note that a
    hardware reset
    during the
    sector erase operation immediately terminates the operation. The Sector Erase
    command sequence should be reinitiated once the device has returned to reading
    array data, to ensure data integrity.
    When the Embedded Erase algorithm is complete, the device returns to reading
    array data and addresses are no longer latched. The system can determine the
    status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to
    “Write Operation Status”
    for information on these status bits.)
    Figure 5
    illustrates the algorithm for the erase operation. Refer to the
    Erase/Pro-
    gram Operations
    tables in the
    “AC Characteristics”
    section for parameters, and to
    Figure 18
    for timing diagrams.
    Erase Suspend/Erase Resume Commands
    The Erase Suspend command allows the system to interrupt a sector erase oper-
    ation and then read data from, or program data to, any sector not selected for
    erasure. This command is valid only during the sector erase operation, including
    the 50 μs time-out period during the sector erase command sequence. The Erase
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