參數(shù)資料
型號(hào)： S29AL016M10BAIR20
廠商： SPANSION LLC
元件分類： DRAM
英文描述： Quad 2-Channel Analog Multiplexer/Demultiplexer; Package: PDIP-16; No of Pins: 16; Container: Rail; Qty per Container: 500
中文描述： 1M X 16 FLASH 3V PROM, 100 ns, PBGA48
封裝： 6 X 8 MM, FBGA-48
文件頁(yè)數(shù)： 33/59頁(yè)
文件大?。?/td> 1917K
代理商： S29AL016M10BAIR20
April 21, 2004 S29AL016M_00A4
S29AL016M
34
Write Operation Status
The device provides several bits to determine the status of a write operation:
DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table
12
and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method
for determining whether a program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Algorithm is in progress or completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final WE# pulse in the program
or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 μs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to
the complement/true datum output described for the Embedded Program algo-
rithm: the erase function changes all the bits in a sector to “1”; prior to this, the
device outputs the “complement,” or “0.” The system must provide an address
within any of the sectors selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 μs, then the
device returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ7–DQ0 on the
following
read cycles. This is because
DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is
asserted low.
Figure 19
, Data# Polling Timings (During Embedded Algorithms),
in the
“AC Characteristics”
section illustrates this.
Table
12
shows the outputs for Data# Polling on DQ7.
Figure 7
shows the Data#
Polling algorithm.
相關(guān)PDF資料
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參數(shù)描述
S29AL016M10BAIR22 制造商:SPANSION 制造商全稱:SPANSION 功能描述:16 Megabit (2 M x 8-Bit/1 M x 16-Bit) 3.0 Volt-only Boot Sector Flash Memory Featuring MirrorBit⑩ Technology
S29AL016M10BAIR23 制造商:SPANSION 制造商全稱:SPANSION 功能描述:16 MEGABIT (2M X 8 BIT / I M X 16 BIT) 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY
S29AL016M10BFI010 制造商:SPANSION 制造商全稱:SPANSION 功能描述:16 Megabit (2 M x 8-Bit/1 M x 16-Bit) 3.0 Volt-only Boot Sector Flash Memory Featuring MirrorBit⑩ Technology
S29AL016M10BFI012 制造商:SPANSION 制造商全稱:SPANSION 功能描述:16 MEGABIT (2M X 8 BIT / I M X 16 BIT) 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY
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