參數(shù)資料
型號: S29AL016M10BAIR13
廠商: SPANSION LLC
元件分類: DRAM
英文描述: Quad 2-Channel Analog Multiplexer/Demultiplexer; Package: PDIP-16; No of Pins: 16; Container: Rail; Qty per Container: 500
中文描述: 1M X 16 FLASH 3V PROM, 100 ns, PBGA48
封裝: 6 X 8 MM, FBGA-48
文件頁數(shù): 44/59頁
文件大?。?/td> 1917K
代理商: S29AL016M10BAIR13
45
S29AL016M
S29AL016M_00A4 April 21, 2004
AC Characteristics
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the
“Erase and Programming Performance”
section for more information.
3. If a program suspend command is issued within t
POLL
, the device requires t
POLL
before reading status data, once
programming has resumed (that is, the program resume command has been written). If the suspend command was issued
after t
POLL
, status data is available immediately after programming has resumed. See Figure 15.
Parameter
Speed Options
JEDEC
Std
Description
90
100
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
90
100
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
DVWH
t
DS
Data Setup Time
Min
35
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OES
Output Enable Setup Time
Min
0
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHWL
t
WPH
Write Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
18
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
t
VCS
V
CC
Setup Time (Note 1)
Min
50
μs
t
RB
Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
100
ns
t
POLL
Program Valid Before Status Polling (Note 3)
Max
4
μs
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