參數(shù)資料
型號(hào)： S25FL004AOLNFI003
廠商： Spansion Inc.
英文描述： 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述： 4兆位閃存的CMOS 3.0伏，50赫茲SPI總線接口內(nèi)存
文件頁(yè)數(shù)： 20/39頁(yè)
文件大小： 945K
代理商： S25FL004AOLNFI003
18
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e I n f o r m a t i o n
WEL bit:
The Write Enable Latch (WEL) bit indicates the internal Write Enable
Latch status. When set to 1, the internal Write Enable Latch is set; when set to
0, the internal Write Enable Latch is reset and no Write Status Register, Program
or Erase instruction is accepted.
WIP bit:
The Write In Progress (WIP) bit indicates whether the memory is busy
with a Write Status Register, Program or Erase cycle. This bit is a read only bit
and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in
progress, if it is 0, no such cycle is in progress.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to
the Status Register. Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction
is decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select
(CS#) Low, followed by the instruction code and the data byte on Serial Data
Input (SI).
The instruction sequence is shown in
Figure 8
.
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b1 and
b0 of the Status Register. Bits b6 and b5 are always read as 0.
Chip Select (CS#) must be driven High after the eighth bit of the data byte is
latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register
cycle (whose duration is t
W
) is initiated. While the Write Status Register cycle is
in progress, the Status Register may still be read to check the Write In Progress
(WIP) bit value. The Write In Progress (WIP) bit is 1 during the self-timed Write
Status Register cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) is reset.
The WRSR instruction enables the user to select one of seven levels of protection.
The S25FL004A is divided into eight array segments. The top eighth, quarter, half,
or all of the memory segments can be protected (as defined in
Table 1, on
page 7
). The data within a selected segment is therefore read-only. The Write
Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W#) sig-
nal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal
allow the device to be put in the Hardware Protected Mode (HPM). The Write Sta-
tus Register (WRSR) instruction cannot be executed once the Hardware Protected
Mode (HPM) is entered.
Figure 8. Write Status Register (WRSR) Instruction Sequence
High Impedance
MSB
Instruction
Status
Register In
CS#
SCK
SI
SO
0 1
2 3
4
5 6
7
8 9 10 11 12 13 14 15
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