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參數(shù)資料
| 型號： | S2204 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad GigaBit Ethernet Transceiver(帶鎖相環(huán)時鐘合成器的四千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 四個千兆以太網(wǎng)收發(fā)器（帶鎖相環(huán)時鐘合成器的四千兆位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 6/33頁 |
| 文件大小： | 339K |
| 代理商： | S2204 |
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6
QUAD GIGABIT ETHERNET DEVICE
S2204
October 9, 2000 / Revision E
TRANSMITTER DESCRIPTION
The transmitter section of the S2204 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Four channels are
provided with a variety of options regarding input
clocking and loopback. The transmitters operate at
1.250 GHz, 10 or 20 times the reference clock fre-
quency.
Data Input
The S2204 has been designed to simplify the paral-
lel interface data transfer and provides the utmost in
flexibility regarding clocking of parallel data. The
S2204 incorporates a unique FIFO structure on both
the parallel inputs and the parallel outputs which en-
ables the user to provide a “clean” reference source
for the PLL and to accept a separate external clock
which is used exclusively to reliably clock data into
the device.
Data is input to each channel of the S2204 nominally
as a 10 bit wide word. An input FIFO and a clock
input, TBCx, are provided for each channel of the
S2204. The device can operate in two different
modes. The S2204 can be configured to use either
the TBCx (TBC MODE) input or the REFCLK input
(REFCLK MODE). Table 1 provides a summary of
the input modes for the S2204.
Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the 125 Mbps 10-bit interface.
The TBC signal is used to clock the data into an
internal holding register and the S2204 synchronizes
its internal data flow to insure stable operation. How-
ever, regardless of the clock mode, REFCLK is al-
ways the VCO reference clock. This facilitates the
provision of a clean reference clock resulting in mini-
mum jitter on the serial output. The TBC must be
frequency locked to REFCLK, but may have an arbi-
trary phase relationship. Adjustment of internal tim-
ing of the S2204 is performed during reset. Once
synchronized, the user must insure that the timing of
the TBC signal does not change by more than
±
3 ns
relative to the REFCLK.
Figure 6 demonstrates the flexibility afforded by the
S2204. A low jitter reference is provided directly to
the S2204 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. The frequency of this output is con-
stant at the parallel word rate, 1/10 the serial data
rate, regardless of whether the reference is provided
at 1/10 or 1/20 the serial data rate. This clock can be
buffered as required without concern about added
delay. There is no phase requirement between
TCLKO and TBCx, which is provided back to the
S2204, other than that they remain within
±
3 ns of
the phase relationship established at reset.
The S2204 also supports the traditional REFCLK
clocking found in many Gigabit Ethernet applications
and is illustrated in Figure 7.
Half Rate Operation
The S2204 supports full and 1/2 rate operation for all
modes of operation. When RATE is LOW, the S2204
serial data rate equals the VCO frequency. When
RATE is HIGH, the VCO is divided by 2 before being
provided to the chip. Thus the S2204 can support Gi-
gabit Ethernet and serial backplane functions at both
full and 1/2 the VCO rate. See Table 3.
Parallel to Serial Conversion
The 10-bit parallel data handled by the S2204 device
should be from a DC-balanced encoding scheme, such
as the 8B/10B transmission code, in which information
to be transmitted is encoded, 8 bits at a time, into a 10-
bit transmission character and must be compliant with
IEEE 802.3z Gigabit Ethernet.
The 8B/10B transmission code includes serial encod-
ing and decoding rules, special characters, and error
control. Information is encoded, 8 bits at a time, into a
10 bit transmission character. The characters defined
by this code ensure that short run lengths and enough
transitions are present in the serial bit stream to make
clock recovery possible at the receiver. The encoding
also greatly increases the likelihood of detecting any
single or multiple errors that might occur during the
transmission and reception of data
1
.
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
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