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參數(shù)資料
| 型號： | S2073 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Five Port Bypass and Repeater for FC-AL(用于FC-AL的五端口旁路電路和中繼器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 159K |
| 代理商： | S2073 |
3
FIVE PORT BYPASS AND REPEATER FOR FC-AL
S2073
February 9, 2000 / Revision D
DEVICE DESCRIPTION
The S2073 provides a port bypass function for up to 5
nodes in an FC-AL circuit, with low jitter accumulation.
An integrated repeater reduces jitter and restores sig-
nal amplitude levels for optimal signal integrity. Jitter
performance of the PLL is specified by jitter tolerance
and jitter transfer. In accordance with ANSI X3T11,
jitter tolerance is divided into random, deterministic,
and frequency dependent jitter. Figure 3 illustrates the
components of random, deterministic, and frequency
dependent jitter that must be tolerated to be ANSI
X3T11 compliant.
Random Jitter Tolerance
Random Jitter Tolerance is the amount of jitter with a
gaussian distribution that the clock recovery PLL must
tolerate.
Deterministic Jitter Tolerance
Deterministic Jitter Tolerance is the amount of Deter-
ministic jitter that the clock recovery PLL must tolerate.
Frequency Dependent Jitter Tolerance
Frequency Dependent Input jitter tolerance is defined
as the peak to peak amplitude of sinusoidal jitter ap-
plied on the input signal that causes the clock recovery
PLL to violate BER specifications. See Figure 4.
Jitter transfer
Jitter transfer is defined as the ratio of jitter on the
output signal to the jitter applied on the input signal
versus frequency. Jitter transfer requirements are
shown in Figures 4 and 5. The measurement condition
is that input sinusoidal jitter up to the mask level in
Figure 4 is applied and the output jitter is measured for
compliance to the mask of Figure 5. The jitter transfer
mask includes specifications for both jitter peaking and
bandwidth.
Lock detect
The S2073 lock detect circuit monitors the selected
input signal to detect the presence of the channel.
This is done by monitoring the frequency content of
the incoming data. The frequency monitor circuit
checks the difference between the divided down re-
covered clock and the externally supplied reference
clock (REFCLK). If the frequency difference between
the recovered clock and the reference clock varies
by more than
±
100 ppm the part will be declared out
of lock. In the out of lock state, the PLL will lock to
the local reference clock and periodically poll the
serial data inputs looking for data with valid fre-
quency content.
Figure 3. Input Jitter Tolerance
Figure 5. Jitter Transfer Specification
Figure 4. Frequency Dependent Jitter
Tolerance Mask
f
/25,000
(42.5 kHz)
Cut-off Freq A
f
/1,667
(637 kHz)
Cut-off Freq B
T
1.5
0.4
Frequency (Hz)
(kHz) = Cut-off Freq @ 1,0625 Gbps
F
D
R
10
-12
0
329
612
940
PS
BER
Jitter
Transfer
Acceptable Range
slope = -20 dB/decade
fc = 2 MHz
Peaking = 0.2 dB
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